1. Field of the Invention
The invention relates generally to Phase Locked Loop ("PLL") circuits and, more particularly, to a lock condition detector for use with a phase locked loop. The invention also relates to a method of detecting a lock condition in a PLL circuit.
2. Description of the Prior Art
PLL circuits are used in a variety of applications including microprocessors, digital video systems, and mobile communication devices, such as cell phones. A PLL circuit is used where a clock signal needs to be generated and synchronized to another source, such as an external reference signal. In its most basic form, as illustrated in FIG. 1, a PLL circuit includes a voltage controlled oscillator ("VCO") 10, which is an oscillator that can run over a range of frequencies dependant on a control voltage applied to a control terminal of the VCO. The VCO is driven by a phase error between the output of the VCO and a reference signal ("REF"), measured by a loop phase comparator 20. This error is used to change the control voltage in such a way that the error between the reference signal and the output of the VCO is reduced, with the goal of maintaining the output of the VCO the same as the reference signal with respect to phase and frequency. Typically, the PLL includes a filter 30 in the control voltage path to provide stability to the control loop. Additionally, by inserting a loop divider 40 between the phase comparator and the VCO, the output of the VCO can be made to be a multiple of the reference signal. The above illustrates the most basic form of a PLL. Examples of some advanced designs of PLL circuits are shown, for example, in U.S. Pat. Nos. 5,349,613; 5,475,718 and 5,349,613 and EP 0 433 120 A1.
Despite advances in control mechanisms, it still occurs that the output signal of the VCO becomes out of lock with respect to the reference signal. Out of lock means that the output signal of the VCO differs from the reference signal with respect to phase and/or frequency by a predetermined factor relevant to the application that the PLL is being used for. This typically occurs temporarily over a few clock cycles as a result of inherent delays in the feedback path. This may also occur, for example, because it takes a finite time for the output of the VCO to change in response to a change in the reference signal. In certain applications, it is desirable that the device, in which the PLL is used, either perform a certain function or not perform a certain function if the PLL goes out of lock. For example, in microprocessors, an indication of PLL lock is useful when the microprocessor is starting up from a power-off state. Until the PLL has locked onto the correct frequency, the microprocessor is held in a reset state to prevent incorrect operation due to spurious clocks of the wrong frequency. This is particularly important when time (i.e. frequency) critical devices such as UARTs or communication devices are controlled by the microprocessor.
Accordingly, it is an object of the invention to provide a lock detection circuit which indicates when two signals are out of lock.
It is another object of the invention to provide such a circuit which generates a signal when the out of lock condition is detected to control the operation of a device containing the PLL.
Yet another object of the invention is to provide a topology for a lock detector circuit which gives great flexibility to a circuit designer in defining and implementing the lock condition.